Coding apparatus and decoding apparatus for transmission/storage of information

ABSTRACT

An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.

BACKGROUND OF THE INVENTION

The present invention relates to a system for transmitting and/orstoring information through a medium of high error rate such as radiotransmission path, and more specifically to a coding and/or decodingapparatus for coding a bitstream obtained by a high efficiencycompression coding to an error correction and/or detection code and fortransmitting and/or storing the coded bitstream.

In a system for transmitting audio and/or video signals via radiotransmission path after the signals have been compression-coded at ahigh efficiency to reduce the signal quantity as small as possible, forinstance as with the case of radio TV telephone, portable informationterminal, digital TV broadcasting system, etc., since the error rate ofthe transmission path is relatively high, it is important to transmitthe obtained bitstream in as high a quality as possible.

When the bitstream is transmitted and/or stored via a medium of higherror rate as described above, an error correction code such as BCHcode, RS code, convolution code, etc. has been so far widely adopted asmeans for reducing the error rate. On the other hand, as means fordetecting an error on the reception side, an error detecting code suchas check sum, CRC, etc. are used. In these error correction and/or errordetection methods, error is corrected and/or detected by addingexcessive (redundant) bits to information to be transmitted and/orstored in accordance with a prescribed rule and further by checkingwhether the transmitted and/or stored bitstream abides by the same rulewhen decoded.

However, in the above-mentioned method such that the bitstream obtainedby high efficiency compression coding is further coded to an errorcorrection and/or detection code and then transmitted and/or stored,there exists a problem in that it is difficult to combine this methodwith a resynchronization method for recovering a synchronization whensynchoronization-loss occured due to an erroneous bistream word causedby the transmission and/or storage medium. Here, as the above-mentionedsynchronization restoring method, there has been widely used such amethod of inserting a unique word (referred to as synchronization codeor start-code) decodable uniquely (unconditionally) and of resumingdecoding operation, in case of synchronization-loss, from a time pointwhen the synchronization code is detected again.

In order to form the synchronization code as a code word decodableunequivocally, it is necessary to construct the code word in combinationwith another code word in such a way that a bit pattern the same as thatof the synchronization code will not appear. In the case of the generalerror correction and/or detection coding method, however, it isdifficult to construct the code word in such a way that a specific bitpattern will not appear. On the other hand, when the bit pattern thesame as the synchronization code appear, pseudo-synchronization mayoccur due to an erroneous detection of the synchronization code.

To overcome this problem, conventionally, the following method has beenso far used: after the error correction and/or detection coding has beenexecuted, the presence of the bit pattern the same as that of thesynchronization code is checked in the bitstream; when the same bitpattern exists, stuffing bits are inserted into the pattern inaccordance with a prescribed rule; and the inserted stuffing bits areremoved in accordance with the same prescribed rule by the decodingapparatus in order to prevent the pseudo-synchronization. In thismethod, however, when the bitstream having an error is transmittedand/or stored, since there exists a possibility that the stuffing bitsare also inserted erroneously, there still exists another problem inthat an additional synchronization-loss or pseudo-synchronization mayoccur.

Further, when the bitstream is coded for error correction and/ordetection and further the synchronization code is inserted, in theconventional method, since many insertion bits must be added to thebitstream at the last portion of a synchronization block sandwichedbetween two synchronization codes in order to compensate for a remainderof the information bits to be coded for error correction and/ordetection, there arises another problem in that the coding efficiency islowered.

On the other hand, in order to increase the error correction and/ordetection capability, although it may be considered to increase theredundancy of the information to be transmitted and/or stored, in thiscase, however, the number of necessary bits increases when the samequantity of the information is transmitted. Therefore, when the errorcorrection and/or detection capability is simply increased, there arisesanother problem in that a transmission path of higher transmission rateis required or that the number of bits of information to be stored isincreased. Further, when the transmission rate or the storage capacityis the same, the quantity of information to be transmitted and/or storeddecreases with increasing redundancy. As a result, in the case whereaudio and video information are compression-coded at a high efficiencyand then transmitted and/or stored, if the redundancy is simplyincreased to increase the error resistance, as far as the transmissionand/or storage rate is the same, since the information must becompression-coded down to a lesser information quantity, there causesanother problem in that the audio quality and picture quality bothdeteriorate.

To overcome the above-mentioned problems, as the method of obtaining ahigh error resistance in spite of a lesser redundancy, there exists amethod referred to as hierarchical coding. In this method, the audio orpicture information compression-coded at a high efficiency is classifiedaccording to the degree of error which deteriorates the audio quality orthe picture quality; the error correction and/or detection code of ahigh redundancy and thereby a high error correction and/or detectioncapability is adopted for the information with more importance and alarge error influence; and the error correction and/or detection codingof a low redundancy and thereby a low error correction and/or detectioncapability is adopted for the information with less importance and asmall error influence. In this method, it is possible to increase theerror resistance in spite of a relatively small averaged redundancy, ascompared with when a correction and/or detection code is used uniformlyfor all the information in the same redundancy.

For instance, in the case of the coding method such that motioncompensation prediction and the orthogonal transform are combined witheach other (which is widely adopted for compression-coding movingpicture information at high efficiency); that is, in the case of thecoding method such that the motion compensation prediction is executedfor the inputted moving picture video signals, and the predictedresidual is orthogonal-transformed (e.g., discrete cosine transform(DCT)), the error correction and/or detection code of strong errorcorrection and/or detection capability is used for the motion vectorinformation or low-order coefficients of the orthogonal transformcoefficients of the prediction residual signals (because theseinformation deteriorates picture quality largely in case an erroroccurs); and the error correction and/or detection code of weak errorcorrection and/or detection capability is used for high-ordercoefficients of the orthogonal transform coefficients of the predictionresidual signals (because these information exerts a relatively smallinfluence upon the picture quality).

To realize the above-mentioned hierarchical coding, it is necessary toswitch the error correction and/or detection codes of different errorcorrection and/or detection capabilities midway in the outputtedbitstream. As the method of switching the error correction and/ordetection codings of different error correction and/or detectioncapabilities, there exists such a method that header informationindicative of the sort of the error correction and/or detection code isadded to the bitstream. FIG. 1 shows an example of a bitstream in whichthe error correction and/or detection codes are switched by addingheader information. In more detail, in this example, two sorts of theerror correction and/or detection codes FETC1 and FEC2 are switched. Ineach of the headers 1101 to 1104, header information indicative of thesort of the error correction and/or detection code and a number of codeword is inserted. Therefore, the coding apparatus arranges the code wordcoded for error correction and/or detection after each headerinformation, and the decoding apparatus decodes the header information;and the decoding apparatus decodes the header information and after thatthe error correction and/or detection code in accordance with thedecoded header information.

However, in the above-mentioned method of switching the error correctionand/or detection codes by adding the header information, however, therearises a problem in that the number of bits of the bitstream to betransmitted and/or stored increases due to the addition of the headerinformation. In the case where audio or video signals arecompression-coded, since some bits are used for the header information,the number of bits used for the compression-coding audio or videosignals is inevitably reduced, with the result that the audio qualityand/or the picture quality inevitably deteriorates.

As described above, when the error correction and/or detection coding isexecuted for a bitstream obtained by compression-coding moving picturesignals, since any bit pattern is generated, in the case where the errorcorrection and/or detection coding is combined with the synchronizationmethod using the unique word as synchronization code, there exists apseudo-synchronization due to erroneous detection of the synchronizationcode. Further, when the stuffing bits are inserted to prevent thepseudo-synchronization, there arises another problem in that thesynchronization-loss and the pseudo-synchronization occur due toerroneous insertion of the stuffing bits.

Further, when the bitstream is coded for error correction and/ordetection and further the synchronization code is inserted, in theconventional method, since a relatively large number of bits must beinserted to compensate for the remainder of the information bits to becoded for error correction and/or detection at the last portion of thesynchronization block, there arises a problem in that the codingefficiency deteriorates.

Further, in the case of the coding and/or decoding apparatus in whichthe error correction and/or detection codes of different errorcorrection and/or detection capabilities are switched by adding headerinformation, since the number of bits to be transmitted and/or storedincreases due to the addition of the header information, when audio orvideo signals are compression-coded at a high efficiency and thentransmitted and/or stored, the information quantity used for audio orvideo information inevitably decreases, with the result there exists aproblem in that the audio quality and the video quality bothdeteriorate.

SUMMARY OF THE INVENTION

With these problems in mind, therefore, it is the first object of thepresent invention to provide a coding and/or decoding apparatus, whichcan solve such a problem as pseudo-synchronization orsynchronization-loss due to erroneous detection of the synchronizationcode, when combined with the resynchronization method which uses boththe error correction and/or detection code and the synchronization code.

Further, the second object of the present invention is to provide acoding and/or decoding apparatus, which can increase the codingefficiency by reducing the number of bits inserted at the last portionof the synchronization block, when combined with the resynchronizationmethod which uses both the error correction and/or detection code andthe synchronization code.

Further, the third object of the present invention is to provide acoding and/or decoding apparatus, which can improve the informationquality by reducing the number of bits of the bitstream to betransmitted and/or stored, without adding header information indicativeof the sort of the error correction and/or detection code, in the casewhen bitstream obtained by compression-coding audio and video signalsare coded by switching a plurality of sorts of error correction and/ordetection codes and then transmitted and/or stored.

To achieve the above-mentioned object, the first aspect of the codingapparatus according to the present invention provides a codingapparatus, comprising: coding means for coding an inputted bitstream toan error correction and/or detection code composed of information bitsand check bits; and bitstream assembling means for assembling anoutputted bitstream by inserting a synchronization code at any one of aplurality of synchronization code insertion positions previouslydetermined in the outputted bitstream, arranging the information bits atany desired positions of the bitstream, and by arranging the check bitsat positions other than the synchronization code insertion positions inthe bitstream.

Further, the first aspect of the present invention provides a decodingapparatus, comprising: synchronization code detecting means fordetecting a synchronization code from a bitstream coded to an errorcorrection and/or detection code composed of information bits and checkbits, at each of a plurality of previously determined synchronizationcode insertion positions thereof; bitstream disassembling means fordisassembling the bitstream to extract the information bits of the errorcorrection and/or detection code and the check bits of the errorcorrection and/or detection code arranged at positions other than thesynchronization code insertion positions; and decoding means fordecoding the error correction and/or detection code on the basis of theinformation bits and the check bits extracted by said code disassemblingmeans.

In the first aspect of the present invention, since the synchronizationcode is arranged at each of a plurality of predetermined synchronizationcode insertion positions in the output bitstream and further since thecheck bits of the error correction and/or detection code are arranged atpositions other than the synchronization code insertion positions, evenif the bit pattern the same as that of the synchronization code isincluded in the check bits, there exists no possibility that thesynchronization code is detected erroneously. Therefore, it isunnecessary to use a specific error correction and/or detection code toprevent a specific bit pattern form being formed or to insert bits toprotect the synchronization pattern after having been coded to the errorcorrection and/or detection code. As a result, it is possible toincrease not only the degree of freedom of selection of the usable errorcorrection and/or detection codes but also to improve the resistanceagainst error, because there exists no possibility that the newerroneous synchronization detection occurs due to mixture of theerroneous insertion bit.

Further, the second aspect of the present invention provides a codingapparatus, comprising: bitstream converting means for converting aninputted bitstream other than a synchronization code arranged at each ofa plurality of synchronization code insertion positions previouslydetermined in an outputted bitstream, in such a way that a Hammingdistance from the synchronization code exceeds a predetermined value;coding means for coding the bitstream converted by said bitstreamconverting means to an error correction and/or detection code composedof information bits and check bits; and bitstream assembling means forassembling an outputted bitstream by inserting a synchronization code atany one of a plurality of the synchronization code insertion positionspreviously determined in the outputted bitstream, arranging theinformation bits at any desired positions of the bitstream, and byarranging the check bits at positions other than the synchronizationcode insertion positions in the bitstream.

Further, the second aspect of the present invention provides a decodingapparatus, comprising: synchronization code detecting means fordetecting a synchronization code at each of previously determinedsynchronization code insertion positions, from a bitstream coded to anerror correction and/or detection code composed of information bits andcheck bits and further including the inserted synchronization codes;bitstream disassembling means for disassembling the bitstream, toextract the information bits of the error correction and/or detectioncode and the check bits of the error correction and/or detection codearranged at positions other than the synchronization code insertionpositions; decoding means for decoding the error correction and/ordetection code on the basis of the information bits and the check bitsextracted by said code disassembling means; and bitstream convertingmeans for converting the bitstream other than the synchronization codearranged at each of the synchronization code insertion positions, whichis decoded by said decoding means and further converted in such a waythat a Hamming distance from the synchronization code in the bitstreamexceeds a predetermined value, to the original bitstream.

In the second aspect of the present invention, since the bit trainarranged at the synchronization code insertion position is converted insuch a way that the Hamming distance from the synchronization codeexceeds a predetermined value and further since the bit train isreversely converted by the decoding processing, the bit pattern the sameas that of the synchronization code will not be included in the bittrain, so that it is possible to prevent the erroneous detection of thesynchronization code. Further, when the bit train is converted in such away that the Hamming distance between the synchronization code and thebitstream other than the synchronization code exceeds a predeterminedvalue, even if an error is mixed with the bitstream, since thesynchronization code can be discriminated from the bitstream other thanthe synchronization code, it is possible to reduce the possibility thatthe synchronization code is detected erroneously.

Further, since the above-mentioned conversion and/or reverse conversionprocessing is executed at the synchronization code insertion positions,it is possible to reduce the overhead, as compared with the prior artmethod such that the conversion and/or reverse conversion processing isexecuted all over the bitstream. In addition, in the case of thebitstream inputted to the coding apparatus, it is unnecessary to executethe conversion processing or to use a special code word, so that the bitpattern the same as that of the synchronization code can be preventedfrom being formed. In particular, in the case where a variable codelength coding apparatus in which different code word tables are switchedin use is connected to the input side of the coding apparatus accordingto the present invention, when the code word table is formed in such away that the bit pattern the same as that of the synchronization codewill not be formed by the variable length coding apparatus, there existsa problem in that the coding efficiency is inevitably reduced. In thepresent invention, however, since the coding apparatus and/or decodingapparatus as described above is used, it is possible to eliminate thisproblem.

Further, the third aspect of the present invention provides a codingapparatus, comprising: coding means for coding an inputted bitstream toan error correction and/or detection code; synchronization codeinserting means for inserting synchronization codes into the inputtedbitstream; deciding means for deciding the number of information bits tobe coded to the error correction and/or detection code and arrangedimmediately before the synchronization code of the bitstream; and saidcoding means forming the error correction and/or detection code arrangedimmediately before the synchronization code as a degenerative codeadaptively degenerated on the basis of the number of bits decided bysaid deciding means.

Further, the third aspect of the present invention provides a decodingapparatus, comprising: decoding means for decoding a bitstream coded toan error correction and/or detection code and further including insertedsynchronization codes; synchronization code detecting means fordetecting the synchronization codes arranged in the bitstream; decidingmeans for deciding the number of information bits coded to the errorcorrection and/or detection code and arranged immediately before thesynchronization code detected by said synchronization code detectingmeans; and said decoding means decoding the bitstream by decidingwhether the error correction and/or detection code arranged immediatelybefore the synchronization code is a degenerative code or not on thebasis of the number of the information bits decided by said decidingmeans.

In the third aspect of the present invention, since a degenerative code(whose number of bits is degenerated to a small number of bits requiredto code the information bits remaining at the last portion of the onesynchronization period (block) is used for the error correction and/ordetection code arranged immediately before the synchronization code, itis unnecessary to use many insertion bits to fill the remainder of theinformation bits at the last portion of the synchronization block, withthe result that the coding efficiency can be increased.

Further, the fourth aspect of the present invention provides a codingapparatus, comprising: coding means for coding an inputted bitstreamincluding a plurality of sorts of information to different errorcorrection and/or detection codes; and switching means for switching thesorts of the error correction and/or detection codes according to thesort of the information included in the bitstream.

Further, the fourth aspect of the present invention provides a decodingapparatus, comprising: decoding means for decoding a bitstream coded toerror correction and/or detection codes of different sorts according toinformation sort, to form original information; and means for decidingthe sort of the error correction and/or detection code on the basis ofthe information sort formed by said decoding means, the decided sortbeing transmitted to said decoding means.

In the fourth aspect of the present invention, when the coding and/ordecoding is executed by switching the error correction and/or detectioncodes according to the sort thereof, since the error correction and/ordetection code is switched on the coding apparatus side according to thesort of information of the bitstream inputted to the coding apparatus,and since the error correction and/or detection code is switched on thedecoding apparatus side by deciding the sort of the error correctionand/or detection code on the basis of the decoded information (i.e., thesame code as that used on the coding side), any header informationindicative of the sort of the error correction and/or detection code isnot required (being different from the prior art method), so that it ispossible to eliminate the overhead due to the header information.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration showing an example of a bitstream obtained bythe prior art error correction and/or detection code switch codingapparatus.

FIG. 2 is a block diagram showing an embodiment of the moving picturecompression coding apparatus according to the present invention;

FIG. 3 is a diagram for assistance in explaining the multiplexing syntaxadopted by a multiplexer of the moving picture compression codingapparatus shown in FIG. 2;

FIG. 4 is a block diagram showing an output coding apparatus of themoving picture compression coding apparatus shown in FIG. 2;

FIG. 5 is an illustration showing an example of an outputted bitstreamoutputted by the moving picture compression coding apparatus shown inFIG. 2;

FIG. 6 is an illustration showing an example of a synchronization code;

FIG. 7 is a block diagram showing the error correction and/or detectionswitching coder of the output coding apparatus shown in FIG. 4;

FIG. 8 is a block diagram showing the bitstream assembler of the outputcoding apparatus shown in FIG. 4;

FIG. 9 is a block diagram showing an embodiment of the moving picturecompression decoding apparatus according to the present invention;

FIG. 10 is a block diagram showing an input decoding apparatus of themoving picture compression decoding apparatus shown in FIG. 9; and

FIG. 11 is a block diagram showing a bitstream disassembler of the inputdecoding apparatus shown in FIG. 10.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described hereinbelow withreference to the attached drawings.

FIG. 2 is a block diagram showing an embodiment of the moving picturecoding apparatus provided with an error correction and/or detectionswitching function according to the present invention, which is combinedwith a compression coding apparatus using motion compensation adaptiveprediction and discrete cosine transform coding (one of orthogonaltransform codings). Here, the coding method in which both the motioncompensation adaptive prediction and discrete cosine transform codingare combined with each other is disclosed in detail by Document: byHiroshi YASUDA, “International Standard of Multimedia Coding”, publishedby Maruzen, June 1991, for instance. Therefore, only the operationthereof will be briefly explained hereinbelow. Further, as the errorcorrection and/or detection code used in this embodiment, such a code asthe BCH code in which the information bits are separated from the checkbits is assumed to be used.

In FIG. 2, moving picture signals 131 to be coded are inputted in unitof frame. The inputted moving picture signals 131 are processed formotion compensation adaptive prediction in unit of small region (e.g.,macro block). In more detail, a motion vector between inputted movingpicture signals 131 and video signals already coded and locally decodedand further stored in a frame memory is detected by a motioncompensation adaptive predictor 101. Further, predicted signals 132 areformed by compensation prediction on the basis of the detected motionvector. In this motion compensation predictor 101, a preferableprediction mode to be used for coding is selected from both the motioncompensation prediction coding and the intra-frame coding (the inputtedmoving picture signal 131 is coded as it is without forming anyprediction signal), and the prediction signals corresponding to theselected mode are outputted.

The outputted prediction signals are inputted to a subtracter 103, andprediction residual signals 133 obtained by subtracting the predictionsignals 132 from the inputted moving picture signals 131 are outputted.The outputted prediction residual signals 133 are discrete-cosinetransformed (DCTed) in unit of constant size block by a discrete cosinetransform section 104, so that DCT coefficients can be formed. Theformed DCT coefficients are quantized by a quantizer 105. The DCTcoefficient signals quantized by the quantizer 105 are branched intotwo. One is variable-length coded by a first variable length coder 106.Further, the other is dequantized by a dequantizer 107, and furtherreversely discrete-cosine transformed by a inverse discrete cosinetransform section 108. The output of the inverse discrete cosinetransform section 108 is added to a prediction signal 132 by an adder109 to form local decoded signals. The formed local decoded signals arestored in a frame memory 102.

On the other hand, the prediction mode and the motion vector informationdecided by the motion compensation adaptive predictor 101 arevariable-length coded by a second variable length coder 110. Thevariable length codes outputted by the first and the second variablelength coders 106 and 110 are multiplexed by a multiplexer 111.

From the multiplexer 111, a bitstream 201 of the multiplexed variablelength codes, an FEC sort ID (identification) signal 202 indicative of asort of the corresponding error correction and/or detection code, and asynchronization code insertion request signal 203 for requesting aninsertion of a synchronization code is outputted.

These signals of the bitstream 202, the FEC sort ID signal 202, and thesynchronization code insertion request signal 203 are inputted to anoutput coding apparatus 200. The output coding apparatus 200 codes thebitstream 201 by switching a plurality of error correction and/ordetection codes of different sorts, to form a final output bitstream205. Here, the output coding apparatus 200 corresponds to the codingapparatus according to the present invention.

FIG. 3 shows a flow of signals multiplexed by the multiplexer 111. Here,the multiplexing is executed in unit frame to be coded. First, thepicture synchronization code 301 is multiplexed. When the picturesynchronization code 301 is multiplexed, the synchronization codeinsertion request signal 203 is outputted from the multiplexer 111 tothe coding apparatus 200, so that the coding apparatus 200 can know thatthe multiplexed code word is a synchronization code. Successively, apicture header 302 indicative of one of various coding modes of thecoded frame is multiplexed upon the bitstream 201. Further, predictionmode information 303 indicative of the prediction mode of the motioncompensation adaptive predictor MC at each region is multiplexed.Further, motion vector information 304 and the DCT coefficients(referred to as residual DCT coefficients) 305 of the predictionresidual signals are multiplexed. Here, when the picture header 302, theprediction mode information 303, the motion vector information 304, andthe residual DCT coefficients 305 are multiplexed, the FEC sort IDsignal 202 indicative of the sort of the error correction and/ordetection code is outputted in correspondence to each of the multiplexedsignals.

Here, an error correction and/or detection code of high correctionand/or detection capability is used for the picture header 302, theprediction mode information 303 and the motion vector information 303,because these information deteriorate picture quality largely when anerror is mixed therewith. On the other hand, in the case of the residualDCT coefficients 305, even if error is mixed therewith, since thepicture quality can be prevented from being deteriorated largely bydetecting the error and by setting the residual to zero, an errorcorrection and/or detection code of high correction and/or detectioncapability is not used; that is, it is sufficient to detect only anerror of the residual DCT coefficients 305.

FIG. 4 is a block diagram showing the output coding apparatus 200 shownin FIG. 2. The output coding apparatus 200 is composed of a bit inserter211, an error correction and/or detection switching coder 212, and abitstream assembler 213. Further, FIG. 5 shows an example of the outputbitstream 205 formed by the output coding apparatus 200. The bitstream205 is composed of a picture synchronization code PSC, a picture headerPH, prediction mode information MODE, motion vectors MV, errorcorrection and/or detection code check bits CHK, residual DCTcoefficients COEF, and stuffing (insertion) bits STUFF. The outputbitstream 205 has the following features:

(1) The picture synchronization code PSC is inserted into any one of thesynchronization code insertion positions as shown by arrows and arrangedat constant intervals (for each sync_period bits). The length of thesync_period is determined larger than the maximum length of thesynchronization code PSC and the maximum length of the check bit CHK.Further, the check bits CHK are arranged each being shifted so as to bearranged immediately before the synchronization code insertion position.

(2) The error correction and/or detection code arranged at the lastportion of one frame (i.e., at the last portion of one synchronizationperiod sandwiched between the two synchronization codes PSC) is apunctured code such that only the finally remaining information bits arecoded. Further, in order to shift the position of the check bit CHK(e.g., the check bit CHK6 in the example shown in FIG. 5,) a necessarynumber of the stuffing bites STUFF are inserted.

(3) The FEC sort ID signal indicative of the sort and the number of theerror correction and/or detection codes is not arranged n the outputbitstream 205 shown in FIG. 5.

In the output bitstream 205 as shown in FIG. 5, since the positions ofthe check bits CHK are shifted as explained in item (1) above, the checkbit CHK is not inserted at any of the synchronization code insertionpositions shown by the arrows in FIG. 5, with the result that thereexists no possibility that the pseudo-synchronization occurs by thecheck bits CHK. Further, in the case of the error correction and/ordetection coding at the last of the frame, although many stuffing bitsmust be inserted at the last of the frame in the prior art method, sincethe punctured code is used for the last of the frame as explained byitem (2) above, it is possible to reduce the number of the insertion(stuffing) bits. In addition, since the header information indicative ofthe sort and the number of error correction and/or detection code is notincluded in the output bitstream 205 as explained by item (3) above, itis possible to reduce the code quantity for the header information.

The construction and the operation of the output coding apparatus 200(shown in FIG. 4) for forming the output bitstream 205 will be describedin more detail hereinbelow in relation between the bitstream 201 shownin FIG. 3 outputted by the multiplexer 111 and the output bitstream 205shown in FIG. 5.

When the synchronization code 301 is multiplexed by the multiplexer 111,the synchronization code insertion request signal 203 is outputted asalready explained. Here, the synchronization code 301 is composed ofsync_(—)0_len bits of “0”, one bit of “1”, and sync_nb_len bits of“xxxxx” indicative of the sort of the synchronization code 301, as shownin FIG. 6. In response to the synchronization code 301 and thesynchronization code insertion request signal 203 outputted by themultiplexer 111, the output coding apparatus 200 outputs thesynchronization code (PSC) of the output bitstream 205 from thebitstream assembler 213.

Here, as shown in FIG. 5, since the synchronization code 301 (PSC) canbe inserted at only the synchronization code insertion positionsarranged at sync_period intervals of the output bitstream 205, when thelast position of the output bitstream 205 already formed is not arrangedat the synchronization code insertion position, the stuffing bits STUFF(as described later) are inserted in such a way that the synchronizationcode 301 can be arranged at the synchronization code insertion position.

After the synchronization code 301 has been outputted to the outputbitstream 205, the picture header 302, the prediction mode information303, the motion vector information 304, and the residual DCTcoefficients 305 are coded as follows: First, bits are inserted into thebitstream 201 outputted by the multiplexer 111 by the bit inserter 211in order to prevent the generation of the pseudo-synchronization. Inother words, when a bit pattern the same as that of the code word of thesynchronization code 301 exists in the output bitstream 205, since thesynchronization code 301 cannot be decoded unequivocally, bits areinserted according to the necessity. For instance, if thesynchronization code 301 is a code word in which the sync_(—)0_len bitsof “0” are arranged continuously as shown in FIG. 6, it is possible toprevent the pseudo-synchronization by inserting “1” in such a way that“0” will not be continued beyond the sync_(—)0_len bits in thebitstream, except at the synchronization code 301.

Here, since the synchronization code 301 is inserted at only thesynchronization code insertion position as already explained, it issufficient when the bit “1” is inserted at only the synchronizationinsertion positions, respectively for prevention of thepseudo-synchronization. Here, a count value 221 indicative of the totalnumber of bits of the output bitstream 205 so far formed is outputted bythe bitstream assembler 213, and further the bit inserter 211 decides asto whether further bit insertion is necessary or not on the basis of thecount value 221 of the bit inserter 211. Here, when the count value 221,that is, the total bit number of the output bitstream 205 so far formedis denoted by total_len, the number of “1” in the bitstream 201 iscounted in a bit block (interval) of0<total_len mod sync_period≦sync_(—)0_len

where A mod B denotes a remainder obtained when A is divided by B.

Here, if there exists no bit of “1” in this bit interval, one bit of “1”is inserted.

Further, in order to reduce the possibility that the synchronizationcode 301 is detected erroneously, bit are inserted as follows:

Here, in order to detect the synchronization code 301 even if an n-biterror is mixed with the synchronization code 301, it is necessary todecide the code word having a Hamming distance less than n from the truesynchronization code, as the synchronization code, by use of an inputdecoding apparatus of the moving picture decoding apparatus (describedlater). In this case, however, if the above-mentioned decision is madeby leaving the bitstream other than the synchronization code 301 as itis, since there exists the case where a bit pattern having a Hammingdistance less than n exists in the bitstream other than thesynchronization code 301, when existing at the synchronization codeinsertion position, this bit pattern is erroneously decided as thesynchronization code 301.

To overcome this problem, the bit inserter 211 inserts bits into thebitstream 201 as follows: the bitstream other than the synchronizationcode arranged at each of the synchronization code insertion positions inthe bitstream 201 is converted in such a way that the Hamming distancethereof from the synchronization code 301 becomes a value larger than2*n+1. In more detail, the number (=n0) of “1” is counted in the bitblock (interval) of0<total_len mod sync_period≦sync_(—)0_len−(2*N+1)

Here, if n0 is less than (2*N+1), {(2*n+1)−n0} bits of “1” are insertedinto the bitstream 201.

After the bits have been inserted by the bit inserter 211 as describedabove, the bitstream 222 is inputted to the error correction and/ordetection code switching coder 212, together with he FEC sort ID signal202 indicative of the sort of the error correction and/or detectioncode.

FIG. 7 is a block diagram showing the error correction and/or detectioncode switching coder 212 shown in FIG. 4 A latch circuit 603 is acircuit for latching the FEC sort ID signal 202, after thesynchronization code has been outputted from the multiplexer 111 to thebitstream 201 and further the synchronization code insertion requestsignal 203 has been outputted. The latched signal 623 is supplied to anerror correction and/or detection coder 604.

The error correction and/or detection coder 604 codes the bitstream 222supplied by the bit inserter 211 for error correction and/or detectionin accordance with the latched signal 623; that is, forms and outputsthe information bits 631 and check bits 632, respectively. Further,after the error correction and/or detection coding for one block hasbeen completed, the error correction and/or detection coder 604 outputsa latch command signal 625 for commanding the latch circuit 603 to latchthe succeeding FEC sort ID signal 202. Therefore, on the basis of thislatch command signal 625, the latch circuit 603 latches the succeedingFEC sort ID signal 202 and supplies the latched signal to the errorcorrection and/or detection coder 604 again.

By repeating the above-mentioned operation, the output coding apparatus200 codes the bitstream 222 (to which bits have been already inserted bythe bit inserter 211) for error correction and/or detection, byswitching the error correction and/or detection codes by the errorcorrection and/or detection switching coder 212 in accordance with theFEC sort ID signal 202 supplied by the multiplexer 111. Here, since theFEC sort ID signal 202 can be latched by the latch circuit 603 only whenthe error correction and/or detection coding of one block has beencompleted, the same error correction and/or detection code is keptapplied until the FEC sort ID signal 202 is switched. For instance, inthe case where the error correction and/or detection code of FEC1 isused for the picture header 302 and the code of FEC2 is used for theprediction mode information 303, if the number of bits of the pictureheader 302 is shorter than that of the one-block information of FEC1,the FEC1 code is kept used for the error correction and/or detectioncode of the succeeding prediction mode information 303 until reachingthe bit number of FEC1 information.

FIG. 8 is a block diagram showing the bitstream assembler 213 shown inFIG. 4. The bitstream assembler 213 is composed of a counter 701 forcounting the number of bits of the output bitstream 205, a buffer 702for storing the check bits 632 and the number of bits thereoftemporarily, a switch 703 for switching the output bitstream 205, and aswitch controller 704 for controlling the switch 703. When thesynchronization code request signal 203 is inputted to the bitstreamassembler 213, the counter 701 is reset to a synchronization code lengthvalue sync_len, and counts up bits in sequence beginning from a bit justafter the synchronization code until the succeeding synchronization codeis inputted. Here, after the synchronization code has bee inputted, theswitch 703 is activated in such a way that the information bits 631 canbe kept outputted until, the first check bit 632 is inputted. When thecheck bit 632 is inputted, the check bit 632 is stored in the buffer702, and the number of bits (check bit number) 711 is outputted from thebuffer 702 to the switch controller 704.

On the basis of the check bit number 711 and the count value 221 of thecounter 701, the switch controller 704 controls the switch 703 to shiftthe check bit, that is, in such a way that the check bit 632 will not beoutputted to the synchronization code insertion position, as alreadyexplained. For instance, when the count value 221 is denoted bybit_count and the check bit number 711 is denoted by check_len, ifbit_count mod sync_period<sync_period−check_leninformation bits 631 are outputted, and ifsync_period−check_len≦total_bits mod sync_period<sync_periodthe check bits 713 stored in the buffer 702 are outputted. After that,the above-mentioned processing is repeated by inputting the informationbits 631 and the check bits 632.

Here, as already explained, since the output coding apparatus 200 usesthe punctured code at the last portion of each frame as the errorcorrection and/or detection code and further shifts the check bitposition for bit insertion, the operation is somewhat different from theordinary operation. In more detail, after having outputted the one-framebitstream 201, the multiplexer 111 first outputs the synchronizationcode insertion request signal 203 for the succeeding frame. Incorrespondence thereto, the error correction and/or detection coder 604of the error correction and/or detection switching coder 212 shown inFIG. 7 regards the insufficient portion of the information bits 631 ofthe error correction and/or detection code, as a bit pattern previouslydetermined and outputted by an insertion (stuffing) bit generator 705,and forms the error correction and detection code by use of theredundant code. Here, the bit pattern can be composed of only bits of“1” or “0” or a repetition of a specific pattern as “010101 . . . ”.

After having outputted the last bit of the information bits 631, in thebitstream assembler 213 shown in FIG. 8, the switch 703 is switched fromthe bit generator 705 to the input side, to insert the insertion(stuffing) bit in such a way that the check bit 713 stored in the buffer702 can be arranged just before the succeeding synchronization code.Here, when the count value 221 of the counter 701 obtained when the lastinformation bit 631 of one frame has been outputted is denoted bytotal_len and the number of bits of the check bits 632 outputted lastlyis denoted by last check_len, the number of the insertion bitsstuffing_len can be expressed asstuffing_len=sync_period−last_check_len−(total_len mod sync_period).

Further, when the degenerative code is not used, the insufficientportion (info_len−last_info_len) from the normal information bitsinfo_len in the last information bits last_info_len are inserted. Inaddition, bits must be inserted in order to shift the check bits. As aresult, as compared with when the redundant code is used, it isnecessary to insert the following additional bits asinfo_len−last_info_len+(info_len−last_info_len) mod sync_period

After having outputted the information bits 631 and the insertion bitsto the output bitstream 205 through the switch 703, the bitstreamassembler 213 is lastly switched to the check bits 731, and outputs theswitched check bits 713 to the output bitstream 205.

The moving picture decoding apparatus according to the present inventionwill be described hereinbelow.

FIG. 9 is a block diagram showing the moving picture decoding apparatuswhich corresponds to the moving picture coding apparatus shown in FIG.2. After having been passed through a transmission and/or storagesystem, the output bitstream 205 outputted by the moving picture codingapparatus shown in FIG. 2 is inputted to an input decoding apparatus 800as an input bitstream 205′. In the present invention, the input decodingapparatus 800 corresponds to the output decoding apparatus 200 accordingto the present invention.

The input decoding apparatus 800, outputs a bitstream 801 obtained bydecoding the error correction and/or detection code, a synchronizationcode detection signal 803, and an error detection signal 804, byswitching the error correction and/or detection code on the basis of anFEC sort ID signal 802 indicative of the sort of the error correctionand/or detection signal applied by the demultiplexer 811. That is, thedemultiplexer 811 inputs the bitstream 801, the synchronization codedetection signal 803, and the error detection signal 804, and outputs aprediction residual signal 841 and a motion compensation adaptiveprediction information code 842, separately.

The prediction residual code 841 is inputted to the first variablelength decoder 806, and the motion compensation adaptive predictioninformation code 842 is inputted to a second variable length decoder810. Residual DCT coefficients 831 decoded by the first variable lengthdecoder 806 are dequantized by a dequantizer 807, inverse-DCTed by ainverse DCT section 808, added to a motion compensation adaptiveprediction signal 832 outputted by a motion compensation adaptivepredictor 801 by an adder 809, and then outputted as reconstructedpicture signals 850. The reproduced picture signals 850 are outputtedfrom the decoding apparatus and further stored in a frame memory 820.Further, the motion compensation adaptive prediction information decodedby the second variable length decoder 810 is inputted to a motioncompensation adaptive predictor 801 to form motion compensationprediction signals 832.

The above-mentioned processing is executed to reproduce moving picturein correspondence to the moving picture coding apparatus shown in FIG.2. Therefore, the serial processing executed by the dequantizer 807, theinverse DCT section 808, the adder 800 and the frame memory 820 as shownin FIG. 9 is basically the same as the serial processing executed by thedequantizer 107, the inverse DCT section 108, the adder 109′ and theframe memory 102 as shown in FIG. 2, although the realizing means aresomewhat different from each other. Further, the processing of the firstand second variable length decoders 806 and 810, the demultiplexer 811and the input decoding apparatus 800 are opposite to the processing ofthe first and second variable length decoders 106 and 110, themultiplexer 111 and the output decoding apparatus 200, respectively,excepting the case where an error injured the bitstream.

FIG. 10 is a block diagram showing the input decoding apparatus 800shown in FIG. 9. The input decoding apparatus 800 is composed of asynchronization detector 901 for detecting the synchronization code ofthe input bitstream 205′, a counter 902 for counting the number of bitsof the input bitstream 205′, a bitstream disassembler 903 fordisassembling the input bitstream 205′ into information bits 912 andcheck bits 913 and for outputting these bits separately, an errorcorrection and/or detection decoder 904, and an inserted stuffing bitremover 905.

The synchronization detector 901 detects the synchronization code atonly the synchronization code insertion position on the basis of thecount value 911 outputted by the counter 902. For instance, when theinterval between the two synchronization code insertion positions isdenoted by sync_period; the count value 911 is dented by bit_count; andthe length of the synchronization code is denoted by sync_len, thesynchronization code is detected only when0<bit_count mod sync_period≦sync_len

Here, it is also possible to detect the synchronization code underconsideration of the presence of an error in the synchronization code.

Here, by the bit inserter 211 of the output coding apparatus 200 shownin FIG. 4, when the bitstream has been converted by inserting bits insuch a way that the Hamming distance thereof from the synchronizationcode becomes 2*n+1 under consideration of an error less than n bits,even if the code having a Hamming distance less than n from the truesynchronization code is decided as the synchronization code, as far asthe erroneous bit is less than n bits, it is possible to prevent thesynchronization code from being detected erroneously.

FIG. 11 is a block diagram showing the bitstream disassembler 903 shownin FIG. 10. The input bitstream 205′ is switched to the information bits1021 and the check bits 913 by a first switch 1002 controlled by acontroller 1001 (described later). When the information bits 1021 areoutputted from the first switch 1002, the information bit length of theinformation bits 1021 are stored by a buffer 1004 via a second switch1003. A counter 1005 counts the number of the output bits from thesecond switch 1003. The count value 1023 of the counter 1005 is comparedwith the information bit length 1024 outputted by an error correctionand/or detection code (i.e., FEC) information output section 1007 by acomparator 1006. When both match, the counter 1005 is reset, and the FECsort ID signal 802 indicative of the sort of the error correction and/ordetection code is latched by a latch circuit 1008. Further, theinformation bits 912 are outputted from the buffer 1004. Further, theoutput 914 of the latch circuit 1008 is inputted to the error correctionand/or detection code information output circuit 1007 and further to theerror correction and/or detection decoder 904 shown in FIG. 10.

As already explained, the check bits of the error correction and/ordetection code are shifted in position so as to be formed between theinformation bits of the error correction and/or detection code arrangedbackward in the bitstream 205. Therefore, the controller 1001 controlsthe switch 1002 in such a way that these position-shifted check bits canbe separated from the information bits. After the information bits ofthe one-block error correction and/or detection code have been inputted,the count value 1023 matches the information bit length 1024 in thecomparator 1006. In response to this match signal, the controller 1001receives the check bit length 1025 from the error correction and/ordetection information output circuit 1007 to calculate the check bitposition inserted between the information bits. Here, when the countvalue 911 indicative of the number of inputted bits of the bitstream205′ (obtained when the comparator 1006 outputs the match signal) isdenoted by bit_count; and the check bit length is denoted by check_len,the check bit start position check_start ischeck_start=(bit_count/sync_period+1)*sync_period−check_lenand the check bit end position check_end ischeck_end=(bit_count/sync_period+1)*sync_periodThat is, the controller 1001 controls the switch 1002 so that the checkbits 913 can be outputted when the count value 911 lies betweencheck_start and check_end.

Further, since the error correction and/or detection coding is executedby the degenerative code at the last of one frame, a special processingis necessary. At the last of one frame, the synchronization detector 901outputs a signal 803 indicative of that the synchronization code of thesucceeding frame has been detected. In response to this signal, thecontroller 1001 calculates the position of the last error correctionand/or detection check bit in the frame and the number of insufficientinformation bits. Here, the assumption is made that the count value 911of the number of bits of the bitstream 205′ inputted when the last errorcorrection and/or detection code of one frame is started to be inputtedis denoted by pre_last_count; the count value 911 at a time when theone-frame bitstream 205′ has been inputted is denoted by total_count;the count value 911 at the processing is denoted by bit_count; the checkbit length of the last error correction and/or detection code of oneframe is denoted by last_check_len; and the check bit length of thesecond-last error correction and/or detection code is denoted bypre_last_check_len. First, since the error correction code is apunctured code and further the bit is inserted, the overs and shorts ofthe information bits are calculated. Here, the number of informationbits last_info_len of the last error correction and/or detection code ofone frame included in the output bitstream 205 islast_info_len=total_count−last_check_len−pre_last_count−pre_last_check_len

Then, when last_info_len is shorter than the information length info_lenof the error correction code, the degenerative code is decided, so thatthe switch 1003 is switched so as to output the bit pattern from theinsertion bit generator 1015 during the period between last_info_len andinfo_len of the count value 1023, in order to supply the insufficientinformation bits due to the degenerative code. Here, the bit patternoutputted by the insertion bit generator 1015 is the same as thatgenerated by the insertion bit generator 705 of the coder shown in FIG.8.

On the other hand, when last_info_len is longer than info_len, thisinformation bit length is decided as inserted bits, and the bit portionof the count value more than info_len is not outputted as theinformation bits 912. On the other hand, the switch 1002 is socontrolled that the output bitstream 205 is outputted as the check bits,when the bit count of the check bits istotal_count−check_len<bit_count≦total_count

The error correction and/or detection decoder 904 inputs the informationbits 912 and the check bits 913 outputted by the bitstream disassembler903, decodes the error correction and/or detection code on the basis ofthe FEC sort ID signal 914 indicative of the sort of the errorcorrection and/or detection code latched by the latch circuit 1008 shownin FIG. 11, and outputs the error-corrected bitstream 915 and theerror-detected signals 804.

The error-corrected bitstream 915 is inputted to the insertion bitremover 905 to remove the insertion bits inserted by the bit inserter211 of the output coding apparatus 200, in order to preventpseudo-synchronization signal from being generated. As alreadyexplained, since the bits are inserted at only the synchronization codeinsertion positions, the synchronization code insertion position can bedecided on the basis of the count value 911 of the counter 902.

For instance, when the synchronization code word is that as shown inFIG. 6 and further when the bits are inserted by the bit inserter 211 at“0000 . . .” portion of the first sync_len bits in such a way that theHamming distance from the synchronization code is more than (2*n+1), thenumber (=n0) of “1” in {sync_(—)0_len−(2*n+1)} bits beginning from thesynchronization code insertion position is counted, when n0 is less than2*n+1, bits of (2*n+1−n0) are removed. Here, however, since theinsertion bits are determined as “1”, when the bit decided by theinsertion bit remover 905 as the insertion bit is “0”, this is regardedas that an error is mixed in the synchronization code insertion block.In this case, therefore, the error detection signal 804 is outputted.

As described above, the bitstream 801 decoded by the input decodingapparatus 800 is reverse multiplexed by the reverse multiplexer 811. Inthis operation, the code word multiplexed as shown in FIG. 3 isseparated and then outputted. Further, this reverse multiplexer 811operates in linkage with the first and second variable length decoders806 and 810, respectively.

In operation in FIG. 9, first when a synchronization code detectionsignal 803 is inputted from the output decoding apparatus 800, thereverse multiplexer 811 is initialized for one-frame processing. Then,the reverse multiplexer 811 outputs the sort of the error correctionand/or detection code corresponding to the picture header, as the FECsort ID signal 802 indicative of the sort of the error correction and/ordetection code, inputs the bitstream 801, and decodes the picture header302 to check whether there exists any error in the decoded pictureheader. When there exists no error, the reverse multiplexer 811 outputsthe sort of the error correction and/or detection code corresponding tothe prediction mode information 303 as the FEC sort ID signal 802,inputs the bitstream 801, multiplexes the prediction mode information,and then outputs the motion compensation adaptive prediction informationcode 842 to the second variable length decoder 810.

When having decoded all the prediction mode information (the motioncompensation adaptive prediction information code 842), the secondvariable length decoder 810 outputs an end signal to the reversemultiplexer 811. In response to this end signal, the reverse multiplexer811 outputs the FEC sort ID signal indicative of the sort of the errorcorrection and/or detection code corresponding to the motion vectorinformation 304, and starts the reverse multiplex processing of themotion vector information 304. The reverse multiplexed motion vectorinformation is outputted to the second variable length decoder 810 fordecoding. After having decoded all the motion vector information, thesecond variable length decoder 810 outputs an end signal to the reversemultiplexer 811. In response to this end signal the reverse multiplexer811 outputs the FEC sort ID signal indicative of the sort of the errorcorrection and/or detection code corresponding to the residual DCTcoefficient 305, reversely multiplexes the residual DCT coefficients305, and outputs the reversely multiplexed results to the first variablelength decoder 806. The first variable length decoder 806 decodes theresidual DCT coefficients 305.

As described above, the sort of the error correction and/or detectioncode is decided by the reverse multiplexer 811 in accordance with themultiplexing rule prescribed in the same way as with the case of theoutput coding apparatus 200. Therefore, it is unnecessary to add theheader information indicative of the sort of the error correction and/ordetection code to the output bitstream 205.

In the error correction and/or detection decoder 904 shown in FIG. 10,there exists the case where a mixture of an error with the inputtedbitstream 205′ can be detected by the error detection code. In addition,there exist the case where an erroneous bit insertion can be detected bythe insertion bit remover 905. In these error cases, the input decodingapparatus 800 outputs an error detection code 804. Further, when a codeword not stored in a variable length word table is detected in thevariable length decoding processing, a mixture of an error is decided.Further, when the presence of a portion departing from the multiplexingrule is decided by the reverse multiplexer 811 during the reversemultiplexing processing, it is discriminated that an error is mixed. Inthese cases, in order to prevent the reproduced picture from beingdeteriorated largely, the input decoding apparatus 800 and the reversemultiplexer 811 execute the following processing:

(1) When an error is detected in the residual DCT coefficient, theresidual at the corresponding portion is set to zero. In this case, whenthe intra-coding mode is selected as the prediction mode, the reproducedpicture signals can be predicted on the basis of the already reproducedframe or the reproduced video signals in the surrounding area.

(2) When an error is detected in the prediction mode information and themotion vector, if it is possible to presume the prediction modeinformation or the motion vector information on the basis of theprediction mode information or the motion vector information existing inthe surrounding area, these information can be used. If impossible,however, the reproduced picture signals are predicted on the basis ofthe reproduced picture signals in the already reproduced frame orexisting in the surrounding area.

(3) When an error is detected in the picture header, since the picturequality deteriorates largely when decoded as it is, the reproducedpicture of the preceding frame is used as it is, as the reproducedpicture of the present frame.

In the above-mentioned processing in the items (1) to (3) above, whenthe error exerts a harmful influence upon the following code till thesucceeding synchronization code, because the variable length coding isused, the similar processing as above is executed for the error-affectedportion.

In the above-mentioned description, an example where the synchronizationcode detector 901 detects the synchronization code at only thesynchronization code insertion positions (for each sync_period bits) hasbeen explained. However, there exists the case where a bit is lost or anerroneous bit is inserted according to the transmission and/or storagemedium. In this case, the synchronization code is detected at theposition other than the synchronization code insertion position, and theposition where the synchronization code can be detected is decided asthe synchronization code insertion position.

Further, in the above description, although an example where the movingpicture is high-efficiency compression-coded and then transmitted and/orstored has been explained by way of example, it is of course possible toapply the coding and decoding apparatus according to the presentinvention to the case where still picture or audio or other informationare transmitted and/or stored. For instance, in the case where stillpicture signals are compression coded at a high efficiency by use of theorthogonal transform, it is preferable to switch the error correctionand/or detection codes in such a way that the lower frequency componentsof the transform coefficients can be protected from error more securely.For instance, in the method of coding audio signals by modeling voicewith a sound source and a sound path filter, it is preferable that theerror correction and/or detection codes are switched in such a way thatthe pitch period and the sound path filter can be protected from errormore securely.

As described above, in the coding and decoding apparatus according tothe present invention, since the synchronization code is inserted atonly the synchronization code insertion position at regular intervalsand further since the check bits of the error correction and/ordetection code are shifted so as to be arranged at a position other thanthe synchronization code insertion position, even if the bit pattern thesame as that of the synchronization code is formed in the check bits,the bit pattern the same as that of the synchronization code will not beformed at the synchronization code insertion position at which thesynchronization code is detected, so that it is possible to perfectlyeliminate the possibility that the synchronization is detectederroneously, from the principle standpoint.

Further, when the bits are inserted into the bitstream arranged at thesynchronization code insertion position in such a way as not to form thepseudo-synchronization, it is possible to eliminate such a prior artdifficulty that the code word must be constructed in such a way that thebit pattern the same as that of the synchronization bits will not beformed.

In addition, in the present invention, since the bits are inserted underconsideration of erroneous synchronization code; that is, since the bittrain arranged at the synchronization code insertion position isconverted in such a way that the Hamming distance from thesynchronization code exceeds a predetermined value and further reverselyconverted by the decoding apparatus, the bit pattern the same as that ofthe synchronization code will not be included in the bit train, so thatit is possible to secure that an erroneous detection of thesynchronization code can be prevented as far as the number of bits isless than a predetermined value. As a result, the possibility of theerroneous detection of the synchronization code can be reduced. Further,when the above-mentioned conversion is executed, even if an error ismixed with the bitstream, since it is possible to discriminate thesynchronization code from the bitstream other than the synchronizationcode, it is possible to reduced the possibility that the synchronizationcode is detected erroneously.

Further, since the error correction and/or detection coding is executedafter the code word has been converted by bit insertion, the bitinsertion can be protected from the error occurrence. Therefore, ascompared with the prior art method such that the bits are inserted afterthe error correction and/or detection coding has been completed, it ispossible to reduce the possibility that the erroneous bit insertionoccurs. In addition, since the bit insertion is executed only at thesynchronization code insertion position, an increase of the codequantity due to the bit insertion can be reduced, as compared with heprior art case where the bits are inserted all over the bitstream, withthe result that the coding efficiency can be increased.

Further, in the present invention, since the error correction and/ordetection code immediately before the synchronization code is formed asa degenerative code, it is possible to reduce the number of insertionbits for compensating for the remainder of the information bitsimmediately before the synchronization code, as compared with the priorart coding apparatus, with the result that the coding efficiency can befurther increased.

Further, in the present invention, since the error correction and/ordetection codes are switched in accordance with the multiplexing rule ofthe high efficiency compression coding apparatus for audio and videosignals and according to the information sort of the inputted bitstream,and further since the error correction and/or detection codes areswitched by deciding the sort of the error correction and/or detectioncode on the basis of the decoded information on the decoding apparatusside, it is unnecessary to add the header information indicative of thesort of the error correction and/or detection code and thereby thenumber of bits assigned to the audio or video high efficiencycompression coding can be increased, with the result that it is possibleto increase the quality of the audio and video information to thatextent.

1.-8. (canceled)
 9. A coding method, comprising: multiplexing aplurality of kinds of variable-length codes generated by compressioncoding of an input image signal to generate a multiplexed code string;assembling an output code string by using the multiplexed code string asan input; and inserting a synchronization code to one of a plurality ofsynchronization code inserting positions periodically predetermined inthe output code string, and inserting a stuffing bit of 8 bits or lessin the output code string.
 10. A coding apparatus, comprising: amultiplexer configured to multiplex a plurality of kinds ofvariable-length codes generated by variable-length coding of an inputimage signal to generate a multiplexed code string; and a codingassembler configured to assemble an output code string by using themultiplexed code string as an input, the coding assembler inserting asynchronization code to one of a plurality of synchronization codeinserting positions periodically predetermined in the output codestring, and inserting a stuffing bit of 8 bits or less in the outputcode string.
 11. The coding apparatus according to claim 10, wherein themultiplexer multiplexes the variable-length codes in units of a frame ofthe image signal.
 12. The coding apparatus according to claim 10,wherein the multiplexer multiplexes the variable-length codes in unitsof a partial area in a frame of the image signal.
 13. The codingapparatus according to claim 10, wherein: the multiplexer multiplexesthe variable-length codes in units of a frame of the image signal; andthe coding assembler inserts the synchronization code to thesynchronization code inserting position located just before or justafter an end portion of each multiplexed portion in the multiplexed codestring, the multiplexed portion being multiplexed in units of the frame.14. The coding apparatus according to claim 10, wherein: the multiplexermultiplexes the variable-length code in units of a partial area in aframe of the image signal; and the coding assembler inserts thesynchronization code to the synchronization code inserting positionlocated just before or just after an end portion of each multiplexedportion in the multiplexed code string, the multiplexed portion beingmultiplexed in units of the partial area.
 15. The coding apparatusaccording to claim 10, further comprising a code string converter whichconverts a code string except for the synchronization code located tothe synchronization code inserting position in the output code string toset a Hamming distance from the synchronization code to be equal to ormore than a predetermined value.
 16. The coding apparatus according toclaim 10, wherein the stuffing bit has a value in which a Hammingdistance between the synchronization code and a portion there is equalto or more than a predetermined value.
 17. The coding apparatusaccording to claim 16, wherein the code string assembler arranges thestuffing bit just before the synchronization code.